1. Field of the Invention
The present invention relates to an in-circuit emulator (abbreviated to ICE from now on) that has an observing function of CPU input/output port signals and an execution control function of programs, for supporting debugging of a system equipped with a CPU.
2. Description of Related Art
FIG. 6 is a block diagram showing a configuration of a conventional ICE together with an internal configuration of an ICE CPU. In FIG. 6, the reference numeral 1 designates an ICE; 2 designates an ICE CPU embedded in the ICE 1; and 3 designates an external trace memory provided outside the ICE CPU 2 for tracing signal logic on input/output ports of the ICE CPU 2. The reference numeral 4 designates an ICE controller for carrying out the execution control of the ICE CPU 2, the control of the external trace memory 3 and the interface with terminal equipment not shown in this figure; 5 designates a processor probe consisting of a cable for connecting the ICE 1 to connection ports of a system board to be debugged; and 6 designates a CPU bus for interconnecting the external trace memory 3, ICE controller 4 and processor probe 5.
In the ICE CPU 2, the reference numeral 11 designates a CPU core 11 constituting a kernel of the ICE CPU 2; 12 designates an internal execution controller for controlling the operation of the CPU core 11; and 13 designates a CPU internal signal output circuit for outputting the internal state of the CPU core 11.
Next, the operation of the conventional ICE will be described.
The CPU core 11 in the ICE CPU 2 is a CPU for carrying out the same operation as that of the CPU on a system board to be debugged. To use the ICE 1, the CPU on the system board is removed, and the input/output ports of that CPU is connected with the ICE 1 via the processor probe 5. Subsequently, the CPU core 11 of the ICE CPU 2 in the ICE 1 is caused to operate in place of the CPU to be debugged.
In the ICE CPU 2, the CPU internal signal output circuit 13 supplies, in synchronism with a clock signal, the external trace memory 3 and the ICE controller 4 with the signal logic on the input/output ports of the CPU core 11, which operates under the execution control of the internal execution controller 12, as CPU internal signals. The external trace memory 3 samples at every clock interval the signal voltage levels of the CPU internal signals fed from the CPU internal signal output circuit 13, and stores the sampled results. Using the external trace memory 3, the ICE 1 implements the observing function of the input/output port signals of the CPU 2.
Techniques relevant to such a conventional ICE are disclosed in Japanese patent application laid-open Nos. 63-188245/1988 and 2-133834/1990, for example.
In the conventional ICE 1 with such a configuration, the number of the chip terminals of the ICE CPU 2 is restricted, and this presents problems of limiting the number of bits of the CPU internal signals that can be output in parallel, and of making it difficult for the external trace memory 3 to sample at every clock interval the signal waveforms of the CPU internal signals output from the CPU internal signal output circuit 13, when the operation frequency of the ICE CPU 2 increases.